Chip Targets’ Circuit Extraction Report is intended to provide our customers a schematic of either whole or parts of a design. By purchasing this analysis, a customer will receive:

(1) A soft copy (jpg format) and a 36” plot of the die montages at each Metal levels and at polysilicon level. Typically, a top level die montage will include pin label, and a polysilicon (or silicon) level die montage will include the component labels. The die montages are obtained by taking stitching together a set of photographs taken at high magnification to allow circuit verification.

(2) A detailed schematic showing all the net connections and the components with appropriate information such as W/L for MOS, emitter area for bipolars, number of squares of resistors, and area for capacitors.